The proliferation of the use of microprocessors in technology has brought with it the need for larger and improved memory packages. More particularly, there is a constant need to increase the density of dynamic random access memories (DRAMs). Memory packages have increased in density from two kilobits of memory cells to present day requirements of over four megabits of memory cells. In designing the DRAM, there are four major priorities. These priorities are: (1) packaging, (2) speed, (3) power, and (4) reliability. With the need for four megabit DRAM cells, these four priorities must be accommodated.
Memory architectures are optimized with respect to all four of these priorities. Efficient layouts and architectures generally dictate that the memory cell dimensions are greater in the direction of the wordline than in the direction of the bitline. The speed associated with the memory cells is directly related to the resistance and capacitance thereof. Any action that reduces the resistance times capacitance product of either the bitline or wordline will improve speed. Similarly, the power associated with the memory cells is related to the capacitance and the speed of operation. Further, increases in capacitance raise delay times associated with the memory cells and therefore diminish the speed of the cell while raising the power requirements therefor.
Incorporation of trenches is a proven technique for improving the density of DRAM memory cells. The practice of total containment of the trench opening within the dimensions of the bitline and wordline prevents the use of minimum width, (i.e. minimum capacitance) bitlines and wordlines. Therefore, a need has arisen for an improved memory cell which accomodates architectural constraints while minimizing capacitances associated with the cell in order to provide a high speed, low power DRAM for a multitude of typical applications.